1. Field of the Invention
The present invention relates to a semiconductor memory device suitably used for, e.g., a memory such as a DRAM.
2. Description of the Related Art
Recently, a semiconductor memory device such as a memory represented by a DRAM or the like, has been required to operate at high speed with low power consumption. In order to attain a reduction of the power consumption in a semiconductor memory device, the power consumption in data write operation should be reduced, for example.
FIG. 1 shows the construction of part of a DRAM. The DRAM is provided with many memory cell arrays on a chip in the form of a matrix. Sense amplifiers are provided for each memory cell array. FIG. 1 representatively shows several sense amplifiers and the corresponding write amplifiers. As shown in FIG. 1, each sense amplifier 10 is connected to the corresponding write amplifier 20 through complementary write global data buses (wgdb, /wgdb) 12 and 13 (the symbol "/" indicates inverted signal).
The sense amplifier 10 has an amplifying section 11 connected to a pair of complementary bit lines (b1, /b1) 18 and 19, a column selection transistor 17 for selecting a column line (CL) 15 in accordance with an address, and a write column selection transistor 16 for selecting a write column line (Write CL) 14 in accordance with an address. The write column line 14 and the column line 15 are commonly connected to the respective gates of the transistors 16 and 17 in sense amplifiers 10 disposed in a column direction.
In this construction, when data is to be written in a memory cell (not shown),"H "-level data is supplied to the gates of the write column selection transistor 16 and the column selection transistor 17 on the basis of an address signal to turn both the transistors 16 and 17 on. The data to be written, which has been amplified by the write amplifier 20, is input to the sense amplifier 10 through the write global data buses 12 and 13, and transferred onto the pair of bit lines 18 and 19 through the respective transistors 16 and 17. The data is then written in the memory cell at the intersection of the pair of bit lines 18 and 19 and the word line (not shown) selected on the basis of the address signal.
As the potential of the "H"-level data output to the pair of bit lines 18 and 19, a power supply voltage Viic for core (for sense amplifier) is used. As the potential for turning the write column selection transistor 16 and the column selection transistor 17 on, and the pre-charge potential for the write global data buses 12 and 13, a power supply voltage Vii for peripheral circuit is used, which is sufficiently higher than the power supply voltage Viic for core.
In the above construction, as a method for reducing the current consumption in a write operation, it is thinkable to set the pre-charge potential for the write global data buses (wgdb, /wgdb) 12 and 13 to half the power supply voltage Vii for peripheral circuit.
In this method, when the write global data buses 12 and 13 are to be restored to the pre-charge state after a write operation, the write global data buses 12 and 13 should be simply short-circuited to make the respective potentials cancel out. The write global data buses 12 and 13 are thereby automatically pre-charged to the 1/2 Vii level. The main power used in this case is only the power for raising the pre-charge potential (1/2 Vii) to the driving potential Vii for write operation when the pre-charge state shifts to a write operation.
But, when a write amplifier 20 is made to perform a data mask operation, i.e., a write amplifier 20 in a row on which data write is inhibited, is inactivated, the following problem arises. The gates of the write column selection transistors 16 and the gates of the column selection transistors 17 in the sense amplifiers 10 disposed in a column direction, are commonly connected through a write column line 14 and a column line 15 in a pair, respectively. For this reason, when an "H"-level signal is supplied to the gates, the transistors 16 and 17 in any of the sense amplifiers 10 become ON.
Consequently, there may be a case that the write column selection transistor 16 and the column selection transistor 17 in a sense amplifier 10 are ON but the corresponding write amplifier 20 is inactivated. In such a case, if the write global data buses 12 and 13 are pre-charged, the potentials 21 and 22 initially generated on the pair of bit lines 18 and 19 on the basis of the power supply voltage Viic for core are influenced by the inactivated write amplifier 20. As a result, both the potentials are attracted to the pre-charge potential 23 of the pair of bit lines and vary, as shown in FIG. 2. If this influence is great, the respective potentials 21 and 22 may be reversed to invert the data values.
For this reason, conventionally, the pre-charge potential for the write global data buses (wgdb, /wgdb) 12 and 13 is set to the power supply voltage Vii for peripheral circuit in order to reduce the influence of disturbance on the potentials of the pair of bit lines 18 and 19, as shown in FIG. 3. In this setting, disturbance appears only in one of the potentials 31 and 32 of the pair of bit lines 18 and 19, and the data values are prevented from being inverted. In this case, however, current consumption increases because the write global data buses 12 and must be pre-charged to the power supply voltage Vii for peripheral circuit, which is a high potential.
As a method for reducing disturbance in the potentials of the pair of bit lines 18 and 19, and also current consumption, it is thinkable to use the power supply voltage Viic for core, which is a power used in the DRAM other than the power supply voltage Vii for peripheral circuit, as the pre-charge potential for the write global data buses 12 and 13, as shown in FIG. 4. This power supply voltage Viic for core is sufficiently lower than the power supply voltage Vii for peripheral circuit and higher than 1/2 Vii.
In this setting, the disturbance in the potentials of the pair of bit lines 18 and 19 can be reduced because a voltage higher than 1/2 Vii is used as the pre-charge potential for the write global data buses 12 and 13. Besides, since it suffices if the write global data buses 12 and 13 are pre-charged to the power supply voltage Viic for core sufficiently lower than the power supply voltage Vii for peripheral circuit, current consumption can be reduced accordingly.
But, when the power supply voltage Viic for core is used as the pre-charge potential, the potential level of the power supply voltage Viic for core, which is less in surplus power than the power supply voltage Vii for peripheral circuit, may vary due to a pre-charge operation. This may impose adverse effects such as noise on a sense operation of the sense amplifier 10 sharing the same power supply. On the other hand, if the power supply voltage Viic for core is increased to take a countermeasure against the noise, the chip size increases.